Reducing Dynamic Power in Booth-Encoded Multipliers Through Zero Representation Selection
This article demonstrates how careful attention to data representation can yield "free" power optimizations with zero hardware overhead.
Hardware/Software Co-Design Lead
Marco Spaziani Brunella
Veteran in the RISC-V CPU Design & Verification space with a focus on AI and Network Packet Processing Accelerators.
About me
I hold a PhD in Electrical Engineering from theĀ University of Rome Tor Vergata. Since September 2016, I have worked on the design and verification of RISC-V processor architectures for Stream Data Processing, and related compiler technology, such as LLVM and MLIR.My PhD Thesis was the culmination of 6 years of research on RISC-based architecture for 100+ Gbps Network Packet Processing.
Starting in November 2021, I fully transitioned to industry, where I led multiple design and verification projects in the RISC-V space, particularly in AI Accelerators and IP Cores.
HereĀ is my latest resume.
Latest posts
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Register Scoreboards: Beyond Simple Forwarding in Pipelined Processors
In this article, we will explore the limitations of operand forwarding and how to effectively use register scoreboards
Mastering External Signal Synchronization in FPGA Design
In the world of FPGA design, few challenges are as fundamental yet critical as handling external asynchronous signals.
Three things I wish I had known before starting a tech startup
It's all about aligning interests.
Work with me
I'm always looking for new opportunities to collaborate and bring ideas to life.