I hold a PhD in Electrical Engineering from the University of Rome Tor Vergata,
I received my B.Sc. and M.Sc. from the same university in Electronic Engineering, with a major in CMOS VLSI and Microwave Systems design.
My main research interest is domain-specific architecture for stream-data processing. I researched offloading architectures for in-kernel network processing functionalities targetting FPGA-based NICs, RISC-V Very-Long Instruction Word CPUs and custom AI-accelerators based on RISC-V SoCs.