Reducing Dynamic Power in Booth-Encoded Multipliers Through Zero Representation Selection
This article demonstrates how careful attention to data representation can yield "free" power optimizations with zero hardware overhead.
Articles
Register Scoreboards: Beyond Simple Forwarding in Pipelined Processors
In this article, we will explore the limitations of operand forwarding and how to effectively use register scoreboards
- 路 FPGA
Mastering External Signal Synchronization in FPGA Design
In the world of FPGA design, few challenges are as fundamental yet critical as handling external asynchronous signals.
- 路 Marco Spaziani Brunella 路 Entrepreneurship
Three things I wish I had known before starting a tech startup
It's all about aligning interests.
How to compile a Large Language Model (LLM) to RISC-V
In this article, we will explore how to compile a Large-Language Model like Bert and generate RISC-V vector extension code
How to generate RISC-V vector code from Tensorflow
In this article, we will explore how to generate RISC-V vector extension assembly from Tensorflow via XLA.
