Open Source & Research

Projects

A collection of open-source projects and research work in RISC-V processor design, FPGA development, and hardware/software co-design.

Tiny Vedas

GitHub

A highly-configurable RISC-V core implementation designed to demonstrate fundamental processor architecture concepts in real, synthesizable SystemVerilog. Features register scoreboards, intelligent pipeline stall management, and multi-cycle operation handling.

RISC-V SystemVerilog Processor Design Computer Architecture

Tiny Vedas eBPF

GitHub

A highly-configurable eBPF core implementation designed to demonstrate fundamental processor architecture concepts in real, synthesizable SystemVerilog. Features register scoreboards, intelligent pipeline stall management, and multi-cycle operation handling.

RISC-V SystemVerilog Processor Design Computer Architecture

ECC-SV Generator

GitHub

A tool to generate SystemVerilog code for Single-Error-Correction/Double-Error-Detection (SEC-DED) modules. Useful for implementing error correction in memory systems and data paths.

Python SystemVerilog Error Correction Memory Systems

SVLib

GitHub

A synthesizable SystemVerilog library for ASIC and FPGA design. Provides reusable components and utilities to accelerate digital design workflows.

SystemVerilog ASIC FPGA Digital Design

External Signal Synchronization Lab

GitHub

A comprehensive FPGA lab demonstrating proper external signal synchronization techniques for clock domain crossing (CDC) and debouncing. Includes practical examples for Xilinx/AMD FPGAs.

FPGA Xilinx Clock Domain Crossing CDC