2023
- A. Trivedi., M. Spaziani Brunella
CPU-free Computing: A Vision with a Blueprint
19th Workshop on Hot Topics in Operating Systems [paper]
2022
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M. Spaziani Brunella, G. Belocchi, M. Bonola, S. Pontarelli, G. Siracusano, G. Bianchi, A. Cammarano, A. Palumbo, L. Petrucci, R. Bifulco.
hXDP: Efficient Software Packet Processing on FPGA NICs.
Communications of the ACM, Vol. 65 [paper, Technical Perspective, Interview] -
M. Bonola, G. Belocchi, A. Tulumello, M. Spaziani Brunella, G. Siracusano, G. Bianchi, R. Bifulco.
Faster Software Packet Processing on FPGA NICs with eBPF Program Warping.
2022 USENIX Annual Technical Conference (ATC) [paper] -
M. Spaziani Brunella, M. Bonola, A. Trivedi.
Hyperion: A Unified, Zero-CPU Data-Processing Unit
Eurosys ‘22 - Systems for Post-Moore Architectures (SPMA) [paper]
2020
- M. Spaziani Brunella, G. Belocchi, M. Bonola, S. Pontarelli, G. Siracusano, G. Bianchi, A. Cammarano, A. Palumbo, L. Petrucci, R. Bifulco.
hXDP: Efficient Software Packet Processing on FPGA NICs.
14th USENIX Symposium on Operating Systems Design and Implementation [paper] Best Paper Award
2019
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S. Pontarelli, R. Bifulco, M. Bonola, C. Cascone, M. Spaziani, V. Bruschi, D. Sanvito, G. Siracusano, A. Capone, M. Honda, F. Huici
Flowblaze: Stateful packet processing in hardware.
16th USENIX Symposium on Networked Systems Design and Implementation [paper] -
M. Spaziani Brunella, G. Bianchi, S. Turco, F. Quaglia, N. Blefari-Melazzi.
Foreshadow-VMM: Feasibility and Network Perspective.
2019 IEEE Conference on Network Softwarization -
M. Spaziani Brunella, S. Turco, G. Bianchi, N. Blefari-Melazzi.
Foreshadow-VMM: on the practical feasibility of L1 cache Terminal Fault attacks.
2019 ITASEC
2018
- M. Spaziani Brunella, S. Pontarelli, M. Bonola, G. Bianchi.
V-PMP: A VLIW Packet Manipulator Processor.
2018 European Conference on Networks and Communications
2017
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M. Spaziani Brunella, S. Pontarelli, F. Marrese, M. Bonola, G. Bianchi.
Packet Manipulator Processor: A RISC-V VLIW core for networking applications. 7th RISC-V Workshop -
A. Nannarelli, M. Re, G.C. Cardarilli, L. Di Nunzio, M. Spaziani Brunella, R. Fazzolari, F. Carbonari.
Robust throughput boosting for low latency dynamic partial reconfiguration.
2017 30th IEEE International System-on-Chip Conference