An eBPF instruction set simulator for hardware verification that parses LLVM-compiled eBPF relocatable object files and generates execution traces in a format that can be used for Hardware verification.

Features

• Parses relocatable ELF object files (.o) compiled from eBPF programs
• Simulates eBPF instruction execution
• Generates execution traces with register and memory updates
• Supports all major eBPF instruction classes:
  • ALU/ALU64 operations (register and immediate)
  • Memory operations (LD, ST, LDX, STX)
  • Jump instructions (JMP, JMP32)
  • Special instructions (EXIT, MOV, etc.)
• Configurable stack pointer (r10) initialization
• Human-readable disassembly matching objdump format

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