A Python-based tool for automatically generating SEC-DED (Single Error Correction, Double Error Detection) encoder and decoder modules in SystemVerilog.

Overview

This tool generates Error Correction Code (ECC) modules that can:

• Detect up to 2 bit errors
• Correct single bit errors
• Support both Even Parity (EP) and Odd Parity (OP) configurations

The generated modules are written in SystemVerilog and follow standard ECC encoding/decoding principles using Hamming codes with an additional parity bit.

Features

• Automatic Generation: Creates both encoder and decoder modules based on input parameters
• Configurable Data Width: Supports any input data size (specified in bits)
• Parity Options: Supports both Even Parity (EP) and Odd Parity (OP) configurations
• Code Formatting: Automatically formats generated SystemVerilog code using verible-verilog-format if installed

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