A tool for generating SystemVerilog instruction decoders from YAML table definitions. This project provides a flexible and maintainable way to define instruction decode tables and automatically generate synthesizable SystemVerilog code.

Overview

Open Decode Tables takes a YAML file describing instruction patterns and their decode outputs, and generates:

• A SystemVerilog module implementing the decoder logic
• A SystemVerilog typedef defining the output structure

This approach separates the instruction decode specification from the implementation, making it easier to maintain and verify instruction decoders for various instruction set architectures.

Features

• YAML-based table definitions: Define instruction patterns and decode outputs in a human-readable format
• Automatic validation: Validates that all decode fields are defined in the output structure
• SystemVerilog generation: Generates synthesizable SystemVerilog code with casez statements
• Flexible pattern matching: Supports wildcard patterns (.) for instruction encoding flexibility
• Multiple backends: Currently supports a native backend (with placeholder for espresso optimization)

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