A complete, open-source implementation of a RISC-V RV32IM processor written in SystemVerilog. Tiny Vedas is a 4-stage pipelined processor with full RV32IM instruction set support, hazard handling, and comprehensive verification.

It is used as a reference for a free course on RISC-V Processor Design.

Features

Architecture

• ISA: RISC-V RV32IM (32-bit integer + multiply/divide)
• Pipeline: 4-stage pipeline (IFU → IDU0 → IDU1 → EXU)
• Data Width: 32-bit (XLEN = 32)
• Memory: Harvard architecture with separate instruction and data memories
• Reset Vector: Configurable (default: 0x80000000)

Instruction Set Support

• Arithmetic: ADD, SUB, ADDI, LUI, AUIPC
• Logical: AND, OR, XOR, ANDI, ORI, XORI
• Shifts: SLL, SRL, SRA, SLLI, SRLI, SRAI
• Comparison: SLT, SLTU, SLTI, SLTIU
• Branches: BEQ, BNE, BLT, BGE, BLTU, BGEU
• Jumps: JAL, JALR
• Memory: LB, LH, LW, LBU, LHU, SB, SH, SW
• Multiply/Divide: MUL, MULH, MULHU, MULHSU, DIV, DIVU, REM, REMU

Advanced Features

• Data Hazard Resolution: Register forwarding from EXU to IDU1
• Control Hazard Handling: Pipeline flush on branches
• Multi-cycle Operations: Pipelined multiplier and divider
• Unaligned Memory Access: Support for byte and half-word aligned loads/stores
• Memory Forwarding: Store-to-load forwarding for performance

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