A complete, fully tested System-on-Chip (SoC) implementation with a CPU that executes the eBPF (extended Berkeley Packet Filter) instruction set architecture. The SoC includes a pipelined eBPF processor, instruction memory, and data memory, all written in SystemVerilog with comprehensive verification.

Features

Architecture

• ISA: eBPF (extended Berkeley Packet Filter) v1.0
• Pipeline: 4-stage pipeline (IFU → IDU0 → IDU1 → EXU)
• Data Width: 64-bit registers (11 registers: R0-R10)
• Memory: Harvard architecture with separate instruction and data memories
• Reset Vector: Configurable

Instruction Set Support

• Arithmetic: ADD, SUB, MUL, DIV, MOD (64-bit and 32-bit variants)
• Logical: AND, OR, XOR
• Shifts: LSH (left shift), RSH (right shift), ARSH (arithmetic right shift)
• Comparison: JEQ, JGT, JGE, JLT, JLE, JNE, JSGT, JSGE, JSLT, JSLE, JSET
• Jumps: JMP, JMP32 (conditional branches)
• Memory: Load/Store operations (8, 16, 32, 64-bit)
  • LD/LDX: Load from memory
  • ST/STX: Store to memory
  • LD64: Load 64-bit immediate (wide instruction)
• Special: MOV, EXIT, CALL, Endianness conversion

Advanced Features

• Data Hazard Resolution: Register forwarding from EXU to IDU1
• Control Hazard Handling: Pipeline flush on branches
• Multi-cycle Operations: Pipelined multiplier and divider
• Unaligned Memory Access: Support for byte and half-word aligned loads/stores
• Memory Forwarding: Store-to-load forwarding for performance

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